The potential of FPGAs as accelerators for high-performance computing applications is very large, but many factors are involved\r\nin their performance.The design for FPGAs and the selection of the proper optimizations when mapping computations to FPGAs\r\nlead to prohibitively long developing time. Alternatives are the high-level synthesis (HLS) tools, which promise a fast design\r\nspace exploration due to design at high-level or analytical performance models which provide realistic performance expectations,\r\npotential impediments to performance, and optimization guidelines. In this paper we propose the combination of both, in order\r\nto construct a performance model for FPGAs which is able to visually condense all the helpful information for the designer. Our\r\nproposed model extends the roofline model, by considering the resource consumption and the parameters used in the HLS tools,\r\nto maximize the performance and the resource utilization within the area of the FPGA. The proposed model is applied to optimize\r\nthe design exploration of a class of window-based image processing applications using two different HLS tools. The results show\r\nthe accuracy of the model as well as its flexibility to be combined with any HLS tool.
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